Imec enables tight standard cell boundary scaling using a two-level semi-damascene integration scheme

The semi-damascene process enables cell boundary scaling down to 8nm tip-to-tip (T2T) in the middle-of-line (MOL) layers, providing self-aligned edges.

A booster that designers can use for packing standard cells tighter, representing a 21 percent area gain over 5T designs.

The novel routing scheme, along with the semi-damascene integration approach, will be critical to gradually push the logic scaling roadmap well into the Å era.

For a long time, the MOL, which provides the connection between the front-end-of-line (FEOL) and back-end-of-line (BEOL), has been organized as a single-layer contact. But currently, it is expanding into several layers, including, for example, the Mint and Vint layers.

These MOL layers carry the electrical signals from the transistor’s source, drain, and gate to the local interconnects and vice versa.

Imec recently introduced a novel standard cell routing architecture called VHV, which involves the introduction of an extra MOL layer (M0B) as a scaling booster to enable 4T standard cell designs.

With this booster, the first three routing layers in the standard cell follow a VHV routing style instead of the traditional HVH routing style in 5T standard cells.

However, the novel two-level MOL VHV scaling booster is challenging from a process integration point of view, mainly arising from the tight boundary between neighboring 4T standard cells.

The cell boundary requires a tight T2T between adjacent MOL M0B lines and two vias (VintB) facing each other with well-defined via edges – all at a minimum distance of one critical dimension (CD) of the top Mint layer.

This means that the T2T and VintB via distance will need to be gradually reduced from ~24nm to ~8nm for upcoming technology nodes. This can no longer be achieved using a direct lithographic print but requires a self-aligned patterning strategy instead.

At IEDM 2022, imec demonstrates how researchers defined the tight boundary between adjacent standard cells using a two-level semi-damascene approach involving a direct metal etch. Zsolt Tőkei, program director of nano-interconnects and fellow at imec: “Roughly speaking, we start from conventionally defined continuous lines and wider vias and, once two metal layers are finished, we split them into two, using the top 16-18nm pitch Mint layer as a hard mask for the final patterning step. This results in 3 edges (of Mint, VintB, and M0B) that are simultaneously self-aligned. With our Ru-based two-level test vehicle, we obtained an average via CD of 10.5nm and M0B T2T as tight as 8.9nm – a key achievement.” Imec researchers complemented structural validation with an initial electrical characterization of line resistance and isolation properties.

“The VHV routing scheme is a critical scaling booster to enable cell boundaries at the A10, A7, A5, A3 technology nodes,” adds Zsolt Tőkei. “It also applies to future device architectures such as nanosheet, forksheet, and CFET. By extending semi-damascene from the BEOL towards the MOL, we have now also found a way to integrate this promising booster. More detailed investigations will, however, be needed, and for that purpose, imec is taping out a new dedicated mask.”