Imperas and Breker partner for Risc-V system-level verification

RISC-V simulation company Imperas Software has announced a partnership with Breker Verification Systems, a provider of test content synthesis for verification environments, to develop interfaces and standards to unify functional verification design flows.

“RISC-V represents an inflection point for semiconductor verification as the design freedoms provided by the open instruction set architecture means an assumption of the responsibility of the processor and system verification task, said Breker CEO David Kelf. “In partnering with Imperas we can offer a combination of technologies and interface standards for IP and SoC testing that ensures commercial-grade verification right through to the end platform.”

Imperas (booths 2336 and 2340) and Breker (booth 2528) will be at the Design Automation Conference (DAC 59) next week in San Francisco.

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